Comments Locked

32 Comments

Back to Article

  • flgt - Thursday, May 17, 2018 - link

    I know people are down on Intel now but they appear to have diversified well (except for the major loss in mobile). They can build a lot of interesting systems even though their manufacturing process and CPU technology has stalled out. Maybe they saw the writing on the wall awhile ago.
  • jjj - Thursday, May 17, 2018 - link

    Look at that, glued together garbage is not a bad thing anymore?
  • sgeocla - Thursday, May 17, 2018 - link

    Glue is so 2017. It's all about EMIB now. Embedded Multi-die Interconnect Binder.
  • HStewart - Thursday, May 17, 2018 - link

    It is so interesting how people are so uneducated about the process especially with this chip and not just about EMiB ( which you are absolutely 100% corrected - it not glue )

    Most people here probably don't understand what FPGA is actually is - it stands for field programmable gate array and it used for custom logic on chip that is programmable. Altera is pretty much the leader in this industry - and in last year or so Intel purchase Altera.

    It probably could be research, but I bet the technology behind EMiB came about because of Intel purchase of Altera, For more information on FPGA there is a wiki on it

    http://theautismchannel.tv/
  • HStewart - Thursday, May 17, 2018 - link

    woops sorry another link was included - from previous conversation

    https://en.wikipedia.org/wiki/Field-programmable_g...
  • CoolDeepBlue - Thursday, May 17, 2018 - link

    Altera was NOT the leader, Xilinx owned/owns more than all the other programmable logic vendors combined together.
    And by the way, the entire industry is NOT using EMIB (or an EMIB like) solution for a reason: it is difficult and expensive (yield)
  • patrickjp93 - Thursday, May 17, 2018 - link

    The industry can't use what Intel keeps to itself. And yields are far better than big interposer solutions. And Intel's Stratix X family destroys everything Xilinx offers. Intel is King of FPGAs now.
  • ZolaIII - Friday, May 18, 2018 - link

    Nope by; market share, internal FPGA interconnect they are behind Xilinx. Only thing they are ahead is a manufacturing process. FPGA's need to become a prime main resident's on heterogeneous and complete SoC's (either with out of much glue or with much better interconnect between glued part's).
  • patrickjp93 - Friday, May 18, 2018 - link

    ??? Intel's latest family is faster on interconnect (58G vs. Xilinx's best 54) with higher integrated compute (10 TFlops vs. Xilinx's best 7), and Intel actually has a coherrent interconnect and system fabric for their designs. Xilinx is years behind now. The only thing Xilinx offers that Intel doesn't is high-speed derivatives trading AICs.
  • BurntMyBacon - Tuesday, May 22, 2018 - link

    Doesn't change the fact that Xilinx is still well ahead by market share. In practice, the 58 vs 54 difference in interconnect speed doesn't usually make much of a difference. Developers are often tied to some standard interconnect (PCIe, SRIO, Fibre Channel, etc.) that both manufacturers have more than enough interconnect bandwidth to support. The compute resources difference is more compelling, but the bulk of development doesn't happen on the top end chips. Many other factors play into it. To name a few: Development Environment (Altera had an edge here, but I'm not sure that is still true), Available IP (Last I checked, Xilinx has the edge here in both free and paid IP), balance of resources (compute units, interconnects, on die memories, fabric, clock generators, etc.), power, and cost.
  • Arnulf - Friday, May 18, 2018 - link

    "and in last year or so Intel purchase Altera."

    Meanwhile in this universe, Intel completed their acquisition of Altera in mid 2015.
  • UltraWide - Thursday, May 17, 2018 - link

    LOL
  • CajunArson - Thursday, May 17, 2018 - link

    Get back to me when AMD finally implements a single piece of silicon that includes more than 8 cores. Since this mid-range chip has 20 cores just in the CPU, let's set the bar low for AMD and only require them to make a single 20 core product.

    "Gluing" together two radically different chips with a high-speed interface in a single package is, yet again, years ahead of what AMD needs to do just to compete with a 2015 Broadwell part.
  • mga318 - Thursday, May 17, 2018 - link

    I mean, yeah, it *is* "years ahead". Trouble is...the performance gap between even a 2013 Haswell and a Skylake chip isn't particularly huge when we consider how many years have gone by. "Years ahead" was a big deal when Moore's Law was still happening...but now? Meh.
  • ZolaIII - Friday, May 18, 2018 - link

    The hole idea about FPGA's is that they are scalable reprogrammable models of the hardware and how you don't need many general purpose CPU's paird with them (which is utterly stupid). FPGA's are good for both high parallel and moderate number of separate simultaneous tasks at the same time & both on separate & more optimal formed hardware blocks on programmable gate's so that they are the best fit for the task. So for instance if you want to accommodate more network IO requests sockets you either build an MIPS TSMP CPU or ASICS or a mix of them on the free gate mesh you don't build (nor use) huge X86 core's. Altera opted for instance for four A53 ARM core's for a reason as they needed general purpose core's only for basic tasks and autonomous operating.
  • Santoval - Friday, May 18, 2018 - link

    Zen 2 next year will probably have 6-core CCXs for 12-core dies, unless they abandon the CCX concept altogether. There's been talk about possible 64-core top server CPUs (4 x 16-core dies), but I don't think they could make 16-core dies with acceptable yields and reasonable sizes at 7nm, unless they develop them specifically for the server and datacenter market.

    AMD chose smaller dies with less cores because this is simply cheaper, with quite better yields. They have less money to burn than Intel and they outsource the manufacturing of CPUs and GPUs. The question is how much faster the link between the dies can become, while still being power efficient, since that is their multi-core performance bottleneck.

    Ryzen 2000 series is faster than Broadwell in single thread performance btw, it is comparable to that of Skylake. Still behind Intel, but not so far behind.
  • ZolaIII - Friday, May 18, 2018 - link

    It still is bad as it's not a complete SoC yet (lacks GPU, HMB) , their is still both IO and latency issue on glued garbage, besides bigger FPGA and less CPU cores are desired.
  • patrickjp93 - Friday, May 18, 2018 - link

    SOCs are not the answer for everything. Try harder.
  • Santoval - Friday, May 18, 2018 - link

    Intel does not use simple glue, they use *super* glue.
  • igavus - Thursday, May 17, 2018 - link

    Considering the price, does the five finger discount still apply?
  • CaedenV - Thursday, May 17, 2018 - link

    initial cost is an arm and leg, but after they find that it is still susceptible to specter it will also cost your your dignity and your job lol
  • modport - Thursday, May 17, 2018 - link

    They announced the discrete PCIe FPGA card ( https://www.altera.com/products/boards_and_kits/de... ) quite some time ago and it looks to still be difficult to purchase. At least, on their site, you can only buy the card if you buy a full server from Dell. Or maybe they only want people who plan to buy in large volumes and hence the need to contact an Intel sales rep.

    It would have been nice if I could buy 1 or 2 PAC cards from their online store, DigiKey, Mouser, etc. for evaluation.
  • A5 - Thursday, May 17, 2018 - link

    I suspect their account team would loan you a card/system if you're a large enough potential purchaser. I suspect we're a year or two away from this getting beyond a special order part.
  • FunBunny2 - Thursday, May 17, 2018 - link

    "Fujitsu is one of the Intel partners planning a system around this processor"

    might that be a mainframe equivalent?
  • pradeepn - Thursday, May 17, 2018 - link

    Who is going to write/design for FPGA ..? Do intel have a list of workloads/partners..
  • patrickjp93 - Thursday, May 17, 2018 - link

    IBM, Amazon, and Google to name a few.
  • ilt24 - Friday, May 18, 2018 - link

    Along with MIcrosoft

    * Microsoft Adds Intel FPGAs to Azure Cloud for AI
    ...https://www.enterprisetech.com/2018/05/08/microsof...

    and

    * Microsoft Beefs Up Bing With Intel FPGAs
    ....https://www.datanami.com/2018/03/27/microsoft-beef...
  • iwod - Friday, May 18, 2018 - link

    price, Arm, Leg lol

    seriously improvement has been slow in recent years. lets hope they pick up pace again.
  • 0ldman79 - Friday, May 18, 2018 - link

    That seriously looks like it is made for a massive communications device, super high end routing, controller for some massive wireless with a dozen devices paired to it, something.

    Looks like it has more IO than CPU power, even counting the 20 cores. Looks like they went with that just to control the IO.
  • wow&wow - Friday, May 18, 2018 - link

    As such a high-end product, does it still have "Meltdown" inside?
  • GreenReaper - Sunday, May 20, 2018 - link

    Better yet, it has a whole new standalone processing unit with built-in cache-coherency protocols with the CPU just waiting for a juicy new compromise!
  • Tiggun - Saturday, May 19, 2018 - link

    I'm curious about what workloads favor fpga acceleration over GPU acceleration? Deep learning comes to mind, but I don't know. The fpga is 14nm, but I wonder if its the same process the Xeon is using. I'd really like to see under the IHS. Does it look like that Intel+Vega underneath

Log in

Don't have an account? Sign up now