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  • levizx - Tuesday, August 6, 2019 - link

    "7nm EUV process node was noted as having started mass production back in October" according to whom?
    Samsung never said anything about mass production, they said production. And the first stage is always risk production.

    And according to Samsung
    https://news.samsung.com/global/samsung-successful...

    "In October 2018, Samsung announced the readiness and its initial production of 7nm process"
    "has started mass production of 7nm process early this year."
    That means Q1 2019.
  • lefty2 - Wednesday, August 7, 2019 - link

    Good catch. Also, it's not first by a very large margin. HiSilicon Kirin 985 which is on TSMC 7nm EUV may launch tommorrow and iPhone 11 (on 7nm Pro) launches in one months time.
  • levizx - Wednesday, August 7, 2019 - link

    7nm wasn't all that dissimilar to 16/14nm except this time it's Samsung who skipped a node and also they had a nodelet as stop-gap.
  • name99 - Wednesday, August 7, 2019 - link

    Everything indicates that Kirin 985 will be 7+, so some EUV levels.
    BUT A13 (next iPhone) is much more iffy, using "7nmPro" which may be simply an optimized version of 7, not using EUV.

    Why the difference? Primarily volume. At the time A13 was finalized, it was probably uncertain whether TSMC could hit Apple volumes on the amount of EUV equipment it had on hand...

    (We've seen similar constraints before on what Apple can do. Even with all that money, there've been times they had to offer a product that lagged slightly behind leading edge because leading edge couldn't supply the volumes Apple needs for every new launch.

    We may even see this in a different form this year with DRAM. It would make sense, technically, for Apple to use LPDDR5 for the new iPhones, but it's unclear whether the various manufacturers can ship enough to make that feasible. It would be natural to design the A13 memory controller to support both LPDDR4 and 5, just to be safe, and it's possible we could see something strange like this year's iPhones use LPDDR4, but the A13X based iPads a few months later use LPDDR5.
    Or even that this year's Apple Watches, in contrast to the phones, use LPDDR5 [for lower power]!)
  • levizx - Thursday, August 8, 2019 - link

    So Apple is using the N7P node instead of N7+. That make sense, N7+ will never have the volume before it's replaced by N6 and N5.
  • name99 - Thursday, August 8, 2019 - link

    Enough with these claims about one node "replacing" another. Talking this way just reveals that you understand fsckall about the Foundry business model.

    TSMC provides a HUGE range of "nodes" for customers. At any one time, one of these is the sexiest (for whatever reason) but that doesn't mean the old ones don't exist. They keep on working, making chips that don't need to be updated every year, or that don't need the newest (and most expensive...) logic.

    TSMC still does a lot of business on 28nm, hell they still DO business on .25µ!
  • levizx - Tuesday, August 13, 2019 - link

    No, you are the one don't understand how it works. N7+ is NOT 28HPx, N7/N7P/N6 are long term nodes, but N7+ will be replaced by N6 and N5, and there will be no more N7+ tapeouts next year. Most of TSMC's 7nm customers won't even migrate to N7+ in the first place, and that includes Apple.
  • eastcoast_pete - Tuesday, August 6, 2019 - link

    Thanks Andrei! In addition to a dress rehearsal of Samsung's EUV process for their own SoCs, I guess this is also a demonstration for other potential fabless customers that Samsung's EUV fab is up-and-running. It'll be interesting to see who bites first.
    @Andrei: I wonder if you heard anything from Samsung about any possible impact, if any, the recent spat between Japan and South Korea has or might have on their ability to churn out wafers by their EUV fab. Apparently, Japan is withholding export permits of several key chemicals needed for the manufacturing of various semiconductors.
  • eldakka - Wednesday, August 7, 2019 - link

    "the chip also had a notable die area disadvantage versus the Snapdragon, coming in at 127mm² versus the smaller 73mm² competition."

    Since the 9825 seems to be pretty much a straight die-shrink, a die area comparison would probably be the most informative. Do we have that data?
  • Anymoore - Wednesday, August 7, 2019 - link

    Interesting, Samsung's release stopped short of any density improvements.
  • Santoval - Thursday, August 8, 2019 - link

    Ninja'd. According to Wikichip Samsung's UHD (Ultra High Density, intended for mobile & low power SoCs) 8nm node variant has a density of ~61 MTr/mm² (MTr = million transistors).
    SemiWiki reports that Samsung's 7nm LPP EUV node will have a "minimum" transistor density of 95 MTr/mm², in other words a 55% higher transistor density.

    Assuming the design of Exynos 9825 is identical to that of 9820, and as it appears it is, and assuming the density will increase by 55% in the entire stack of the SoC (from FEOL to BEOL, not just in FEOL), which is not certain, let's estimate the die area decrease from the 55% increase in density. Let's rather make it a nice round 50% density increase to account for a potential density misalignment in the BEOL stack :

    A doubling of density leads (obviously) to a 50% smaller die area, so a 50% higher density should make the die ~25% smaller. 127 mm² - 25% is ~95 mm². That's still larger than the 73 mm² of the equivalent Snapdragon, but it's quite smaller than 127 mm², with plenty more usable dies per wafer.
  • Anymoore - Wednesday, August 7, 2019 - link

    The EUV tools in use so far have insufficient uptime for manufacturing. So I wouldn't expect a steady volume at this point.
  • name99 - Wednesday, August 7, 2019 - link

    How do you know?
    Seems to me Samsung's decision makers are likely more informed about their EUV uptimes and throughput than what J Random Internet user has managed to glean from year-old conference reports and random tweets.
  • Anymoore - Wednesday, August 7, 2019 - link

    It is from this year's announcement of NXE:3400C by ASML. I don't think Samsung claims high throughput and uptime either.
  • name99 - Wednesday, August 7, 2019 - link

    ASML said no such thing. They actually said "Production and service capability in place to enable
    ASML required volume in time"

    https://staticwww.asml.com/doclib/investor/financi...
    pg 16

    Of course it'a always nice to do things faster, and the C will be a more desirable machine than the B. But ASML said nothing close to what you claim.
  • Anymoore - Wednesday, August 7, 2019 - link

    I got it here: https://semiwiki.com/semiconductor-services/ic-kno...

    So it's not yet at the target, and the C introduction makes it look like large changes are necessary.
  • Santoval - Friday, August 9, 2019 - link

    Samsung's "decision makers" have a vested interest to overpromise their company's prowess, so they are not exactly the most reliable sources. And when you overpromise you underdeliver. Hell, Intel have been doing this since 2015 with their 10nm node, year after year and quarter after quarter, and they still have not released any 10nm fabbed products in the market (that December 2017 limited launch of that half broken dual core Cannon Lake i3, exclusively for some Chinese schools, was not a release, it was a "let's pull the wool over the eyes of our most gullible investors by reporting a nominal 2017 release of a 10nm fabbed CPU" tactic).

    By now you should be suspicious enough to not trust anything EUV related various companies with a vested interest in/from EUV announce, since EUV has been delayed even longer than Intel's 10nm node (that's surely quite a feat!). The EUV situation is still so sketchy companies will insert it only for some non critical layers (apparently the lowest metal layers of the BEOL stack, probably the M0 to M3 layers) at first.

    Evidently the pellicles for the EUV photomasks are not yet as good as the fabs would like them to be, and without pellicles you cannot print anything in the FEOL stack, but you can etch a few layers of the BEOL stack with "bare" masks, at a slight risk of damaging or soiling them. They hope the pellicle issue and some other less serious issues will have been resolved by the time the 5nm node starts HVM though.
  • Arsenica - Wednesday, August 7, 2019 - link

    EUV tools may not be able to replace the volume of 193i tools right now, but as this is just a tweaked version of Samsung's 8nm process they are not using EUV for all high resolution steps.

    We can be pretty sure that they are still using 193i multiple patterning for the fins and the use of EUV is likely limited to contact holes and/or Metal1 (steps in which using EUV is likely to result in increased yields with current technology). So Samsung will likely be able to provide a volume similar to that of their 8nm process.

    EUV tools won't replace 193i tools for FEOL steps before the 5nm-class nodes or maybe until they abandon FinFETs for Gate-all-around FETs
  • Anymoore - Wednesday, August 7, 2019 - link

    Samsung's multipatterning lithography for BEOL is simply inferior compared to their competitor(s); which is why they have so many mask steps.
  • Zingam - Wednesday, August 7, 2019 - link

    AV1 support?
  • ksec - Wednesday, August 7, 2019 - link

    As a consumer you are basically paying for the additional die space for complex AV1 decoding instead of the patents involved in HEVC. And die space hurt SoC's margin.
  • The_Assimilator - Wednesday, August 7, 2019 - link

    A whole 90MHz clock speed increase in a single domain... much wow.
  • danielfranklin - Wednesday, August 7, 2019 - link

    You might find power usage to be a lot better and to be able to hold clocks a lot better, therefore providing better performance than it would appear on paper.
    That said, its the first EUV silicon around, they might suck at it initially...
  • name99 - Wednesday, August 7, 2019 - link

    That's a seriously silly comment. It's clear the point of this exercise is to show that EUV works, not to design a new chip.

    Apple did something similar with the A5. The original was on 45nm, then a die shrink to 32nm which was just to reduce costs and gain 32nm experience, not any attempt to improve the SoC.

    (Apple actually followed that up with a THIRD redesign, also 32nm, this time slightly re-arranging things, to optimize for the last remaining client of the A5, namely the Apple TV at that time. But that's irrelevant to what SS is doing here!)
  • eforfunopen - Wednesday, August 7, 2019 - link

    In October 2018, Samsung announced the readiness and its initial production of 7nm process"
    "has started mass production of 7nm process early this year."
    That means Q1 2019
  • s.yu - Wednesday, August 7, 2019 - link

    So it's more of a tech demonstration by Samsung LSI, no wonder it doesn't seem to make immediate sense economically.
  • name99 - Wednesday, August 7, 2019 - link

    (a) A Tech Demonstration is a few carefully selected chips.
    This is HVM, don't pretend otherwise.

    (b) You have fsckall clue about the economics of this, either on a per-chip basis or longer term.
    Again don't pretend otherwise.

    It's kinda amazing how many people want to dismiss what's a very real achievement by Samsung as some kind of meaningless stunt, implying that either it's not many chips, that they're too expensive for this to be sustainable, or that there's something wrong with the chip performance.
    It's fine to cheer on your team, whether that's Intel or TSMC (or, god help you, GloFo). But if you're not willing to honestly understand and accept what the competition are doing, maybe you should switch to cheering sports or politics --- because you will land up looking like a fool, repeatedly, in the tech context.
  • 0iron - Wednesday, August 7, 2019 - link

    Is there any 7nm LPE from Samsung? It seem odd that first 7nm process is in LPP.
  • levizx - Wednesday, August 7, 2019 - link

    Not really. LPE means *Early* to market. Both 14LPE and 10LPE was the first offering in the market. While 11LPP, 8LPP, 7LPP was not earlier than comparable TSMC/GF offerings.
  • Gondalf - Wednesday, August 7, 2019 - link

    Lets hope EUV run. Samsung could be a good second source to TSMC, this will help the competition lowering the prices of silicon. Looks like confirmed Nvidia will have some production on this process and i have suspect Intel too for its consumer GPUs....and who knows even some consumer Cpus too :).
  • Dragonstongue - Wednesday, August 7, 2019 - link

    competition from the same company to the same company (Samsung/TSMC) is not so much competition now is it?

    unfortunately at this "high level" there are so very very few players that actually hold any cards worth playing.

    also when was last time you heard of a major player doing an across the board "lower price" ... the last company I personally heard of doing so making almost a mantra was AMD with Ryzen "more cores for less $$"

    But as far as Samsung to be a good second source to TSMC, ummmm, yeh, maybe, seeing as Samsung/TSMC/AMD/IBM and a few others are "buddy buddy" chasing the last bit of life silicon has to it, maybe the way they are rushing the so called die "shrinks" TSMC, Samsung etc will be able to go back to 16nm or so and "do it again" to get a true 100% die shrink, not the mix of some stuff gets shrunk and the rest does not.

    anyways....Samsung orders from TSMC, last I heard TSMC does not get anyone to do their FAB work, seeing as THEY do the fab work for others

    LOL
  • levizx - Wednesday, August 7, 2019 - link

    What a stupid comment! TSMC is a PUREPLAY fab. Samsung Group is NOT. Samsung Foundry does not order from TSMC, as THEY do the fab for others.
  • FullmetalTitan - Thursday, August 8, 2019 - link

    This might help you learn something:
    https://www.quora.com/What-does-pure-play-or-IDM-m...
  • Yojimbo - Wednesday, August 7, 2019 - link

    You think Intel will contract Samsung to produce chips for them?! Any source for that or is it just your own speculation?
  • name99 - Wednesday, August 7, 2019 - link

    Why not? Once again, even though the internet seems to think semiconductors is a sports game based on cheering and kayfabe, in the actual world businesses co-operate all the time.

    Intel, for example, bought Infineon. And manufactured modems on TSMC for a few years.

    Intel bought Movidius. And manufactured vision chips on TSMC (I think all Movidius products being sold by Intel are STILL on TSMC, already through one upgrade cycle, and have no idea if they plan to stick with that or change it).
  • Gondalf - Wednesday, August 7, 2019 - link

    Not only, Stratix apart, nearly all the Intel Altera production is on TSMC, moreover Intel Nervana chip is on TSMC process too.
  • Gondalf - Wednesday, August 7, 2019 - link

    Only Logic?? sometimes speculation is useless. A GPU need of a lot of silicon footprint, that silicon not necessary is of very high value because clocks are low and the main problem is to keep leakege down lowering the voltage.
    Why to utilize Intel Fabs for this silicon area?? We don't need of high levels of drive current, far better manufacture GPUs in a Foundry. Internal Fabs are better suited to print server dies and high margins consumer SKUs.
  • Anymoore - Wednesday, August 7, 2019 - link

    Something important missing: https://www.mitsuichem.com/en/release/2019/2019_05...
  • NICOXIS - Wednesday, August 7, 2019 - link

    This die shrink should put it on par with 855 now
  • Anymoore - Wednesday, August 7, 2019 - link

    Applying 40% area reduction (127 * 0.6), would almost catch up.
  • Unserved.tech - Wednesday, August 7, 2019 - link

    The Exynos 5430 only powered the Galaxy Alpha, not the Galaxy S5 (which was powered by exynos 5422)
  • ksec - Wednesday, August 7, 2019 - link

    I think it is important to note Samsung will likely not be dual sourcing SoC after the settlement with Qualcomm. Qualcomm also likely got a very decent Fab deal in the settlement with Samsung, which is something Samsung needed anyway to expand their Fab Capacity.

    So it is a Win-Win for now.
  • ksec - Wednesday, August 7, 2019 - link

    I am not well versed in the Samsung SoC, but why is it 120mm2 die size and perform not as good as a 80mm2 Snapdragon?
  • Otritus - Thursday, November 12, 2020 - link

    A combination of inferior microarchitecture and less dense and less efficient node leads to lower performance at a larger die size.
  • dropme - Thursday, August 8, 2019 - link

    Samsung is like the old Intel in the 80s which had got its place in the DRAM market. They builds Memory but also designs processors and takes fab orders. It's truly fabulous to watch this silicon giant keeps growing and I wonder who would be the one to dethrone them.
  • xian333c - Friday, August 9, 2019 - link

    If 7nm EUV reached that claims to 30% up to 50% lower power , Samsung's M4 will be same performance/W with A76. And A75 with be higher performance/W than A76 middle cores.
  • yeeeeman - Tuesday, August 13, 2019 - link

    Andrei, I guess you will have a comparison between 9820 and 9825, right? It will a very interesting read I expect.
  • NICOXIS - Thursday, August 22, 2019 - link

    That'd be very interesting in deed
  • yankeeDDL - Tuesday, August 13, 2019 - link

    The large difference in die size between the 9820 and the 855 cannot possibly be only due to the difference in density between Samsung 8nm and TSMC 7nm process. A difference in 12% linear, should, ideally, reduce the 9820 from 127mm2 to ~100mm2, not to 73mm2.

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