AMD K7: Speculation

AMD K7 Features

• 0.25 micron process

• 128K L1 cache

• Alpha EV6 compatible, 200mhz front side bus

• 500+mhz initial speed

• 3DNow

• Fully pipelined FPU

• 9 issue superscalar

• Multiprocessor capable

• H1 '99

AMD K7 Features Summarized

Looking at the specifications of the AMD K7, you can probably tell that it is going to pack quite a punch when it makes its way out of the fab. plants and into our systems. The AMD K7 will be made on a 0.25 micron process (0.25 micron = the size of the connections on the silicon wafer) initially, the current state of the art. This process should allow the K7 to run cool enough to reach speeds of 500mhz, but once the K7 reaches higher speeds, such as 700mhz, the 0.25 micron process might not be efficient enough to warrant stability. The 128K L1 cache is one of the more intriguing features of the AMD K7. Current state of the art processors have 64K L1 (The K6(-2) and 6x86MX are examples). L1 cache is where the most frequently used data is stored on the chip. L1 cache has extremely fast access times and is the most efficient place to retrieve data from. (More on cache in bandwidth discussion) Basically, more L1 cache speeds up software significantly, especially highly repetitive software, such as Microsoft Word and spread sheet software. (these programs do the same thing over, and over, and over). AMD, however, doesn't think 128K L1 cache is enough. They plan on using Digital's Alpha EV6 bus to transfer data from RAM to the CPU. The EV6 bus allows for RAM to CPU transfers of up to 200+mhz! (FrontSideBus) yielding a bandwidth of 2.6GB (Gigabytes) / sec.

Another cool feature of the K7 is the fully pipelined FPU, which, according to AMD is supposed to peak at two instructions per clock. If this is true, the K7 will significantly outperform Intel equivalents in FPU intensive applications. 3DNow will of course be implemented, to add to the gaming horse power of the AMD K7.

The K7 will fit in a Slot A, (A Slot similar to Slot 1, but using a different protocol to transfer data (EV6) and house the L2 cache in the cartridge like the Pentium II.

The core is a seventh generation core with advanced scheduling, branch prediction, pipelining and more...